1996/9 ～2000/7 西安交通大学   本科 计算机科学与技术
2000/9 ～2005/7 清华大学   硕士、博士 计算机科学与技术

智能芯片设计/电子设计自动化。研究方向包括存算融合高能效智能芯片架构；基于FPGA的人工智能加速器设计；大规模集成电路优化技术等。 

2019/4 ～至今     中国科学技术大学 副教授
2012/9 ～2019/3 中国科学技术大学 轨道制副教授
2009/4 ～2012/8    日本早稻田大学 助理教授
2008/4 ～2009/3    日本早稻田大学 访问讲师
2005/8 ～2008/3    日本早稻田大学 访问副研究员 

2023 年安徽省教学成果奖 特等奖
2022 年安徽省研究生教学成果奖一等奖(3/15)
2018 年中国科学技术大学校级“优秀博士学位论文”指导老师
2017 年第一届全国大学生集成电路创新创业大赛优秀指导老师（指导学生获全国总决赛二等奖） 

国家自然科学基金面上项目（青年）：应用射频互连的低功耗专用片上网络体系结构综合研究   2015/1~2017/12（主持，结题）
国家自然科学基金面上项目：动态可重构专用片上网络架构综合关键技术研究 2017/1~2017/12 （主持，结题）
国家自然科学基金委面上项目 脑网络启发的大规模神经形态系统片上互连结构综合2019.01-2022.12 (主持)
国家自然科学基金委重点项目子课题 基于忆阻器的大规模神经网络的类脑计算架构研究2018.01-2022.12 (主持)
中国科学院先导B课题 面向智能内存的软件系统2020.1~2024.12（主持）
科技部重点研发计划项目 基于DRAM的存算一体架构   2020.1~2023.12(参与) 

[1] Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen*, Yi Kang. NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43(5), pp. 1456-1469, 2024. 
[2] Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang. Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. IEEE Transactions on Computers, 73(1), pp. 152-163, 2024. 
[3] Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, and Yi Kang. BusMap: Application Mapping with Bus Routing for Coarse-Grained Reconfigurable Array. IEEE Transactions on Circuits and Systems II: Express Briefs. 70(8), pp.  3054 - 3058, 2023.
[4] Mengke Ge, Bingxiao Ni, Song Chen, and Yi Kang, "Generating Brain-Network-Inspired Toplogies for Large-Scale NoCs on Monolithic 3D ICs", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 69, no. 3, pp. 1552-1556, March,2022. 
[5] Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen, "GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3492-3502, Oct. 2022. 
[6] Zhimin Lu, Jue Wang, Zhiwei Li, Song Chen and Feng Wu. A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching. IEEE Transactions on Circuits and Systems for Video Technology, Vol.32, No.2, pp. 660-673, 2022. 
[7] Mengke Ge, Bingxiao Ni, Qi Xu, Jinglei Huang, Song Chen, Yi Kang, Feng Wu, "Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips", ACM Transactions on Design Automation of Electronic Systems, 27(1), 9:1-9:30 2021 (Full Text in ACM DL)
[8] Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, and Feng Wu, "Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems", IEEE Transactions on Automation Science and Engineering (TASE), 2021 (accepted) (Full Text in IEEE Xplore)
[7] Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, and Feng Wu. Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6, pp. 1191-1204, June 2020.
[8] Song Chen, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu, “Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October, Vol.39, No.1, pp.199-212, January 2020.
[9] Song Chen, Qi Xu, Bei Yu, “Adaptive 3D-IC TSV Fault Tolerance Structure Generation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 38(5), pp.949-960,2019.
[10] Qi Xu, Song Chen, Xiaodong Xu, Bei Yu, "Clustered Fault Tolerance TSV Planning for 3D Integrated Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 36, No.8, pp. 1287-1300, Aug. 2017.